What are the three categories of computer architecture?
Every computer, from the simple device to the most complex machine, operates according to its architecture. This architecture – the rules, methods, and procedures that tell the computer system what to do and how to work – can be broken into three main sub-categories.
Instruction set architecture
An instruction set architecture, or ISA, is a collection of instructions that a computer processor reads. It outlines how the central processing unit (CPU) is controlled by its software, and effectively acts as the interface between the machine’s hardware components and its software. In fact, the instruction set architecture provides the only means of interacting with the hardware, visible to assembly language programmers, compilers, and application managers.
There are two main types of instruction classifications:
- Reduced Instruction Set Computer (RISC), which implements only the single instruction formats that are frequently used in computer programmes. These include what’s known as MIPS (microprocessor without interlocked pipelined stages), which was developed by John Hennessy at Stanford University in the 1980s.
- Complex Instruction Set Computer (CISC), which can implement several specialised instructions.
The ISA also defines and supports a number of key elements within the CPU, such as:
Supported data types are defined by the instruction set architecture. This means that through the ISA, a computer will understand the type of data item, its values, the programming languages it uses, and what operations can be performed on or through it.
Registers store short-term data and manage the hardware’s main memory – the random access memory (RAM). They are located within processors, microprocessors, microcontrollers, and so on, and store instructions for decoding or executing commands. Registers include:
- the programme counter (PC), which indicates where a computer is in its programme sequence. The PC may also be referred to as the instruction pointer (IP), instruction address register (IAR), the instruction counter, or the instruction sequencer.
- the memory address register (MAR), which holds the address of an instruction’s related data.
- the memory data register (MDR), which stores the data that will be sent to – or fetched from – memory.
- the current instruction register (CIR), which stores the instructions that are currently being decoded and executed by the central processing unit.
- the accumulator (ACC), which stores the results of calculations.
- the interrupt control register (ICR), which generates interrupt signals to tell the central processing unit to pause its current task and start executing another.
The instruction set architecture outlines how the hardware will support fundamental features, such as:
- Memory consistency models, which essentially guarantee that if a programmer follows set rules for operations on memory, then memory will be consistent, and the results of reading, writing, or updating memory will be predictable.
- Memory addressing modes, which are the methods used for locating data and instructions from the RAM or the cache. Mode examples include immediate memory access, direct memory access, indirect memory access, and indexed memory access.
- Virtual memory, also known as virtual storage, which utilises both hardware and software to allow a computer to temporarily transfer data from RAM to disk.
Also called computer organisation, microarchitecture is an important sub-category of computer architecture. There is an inherent interconnection between the microarchitecture and the instruction set architecture, because the microarchitecture outlines how a processor implements its ISA.
Important aspects of microarchitecture include:
- Instruction cycles. These are the steps required to run programmes: reading and decoding an instruction; finding data associated with the instruction; processing the instruction; and then writing out the results.
- Multicycle architecture. Multicycle architectures are typically the smallest and simplest architectures because they recycle the minimum required number of logic design elements in order to operate.
- Instruction pipelining. Instruction pipelining is a tool for improving processor performance because it allows several instructions to occur at the same time.
System design incorporates all of a computer’s physical hardware elements, such as its data processors, multiprocessors, and graphic processing units (GPUs). It also defines how the machine will meet user requirements. For example, which interfaces are used, how data is managed, and so on. In fact, because of its link with meeting specified user requirements, system design is often mentioned alongside product development and marketing.
Other types of computer architecture
Von Neumann Architecture
Also known as Princeton architecture, the Neumann model of computer architecture was developed by John von Neumann in the 1940s. It outlines a model of computer architecture with five elements:
- A processing unit that has both an arithmetic and logic unit (ALU) as well as processors with attached registers.
- A control unit that can hold instructions in the programme counter or the instruction register.
- Memory that stores data and instructions, and communicates through connections called a data bus, address bus, and control bus.
- External mass storage, or secondary storage.
- Mechanisms for input/output devices.
Harvard architecture uses separate memory storage for instructions and for data. This differs from, for example, Von Neumann architecture, with programme instructions and data sharing the same memory and pathways.
Single instruction, multiple data (SIMD) architecture
Single instruction, multiple data processing computers can process multiple data points simultaneously. This paved the way for supercomputers and other high-performance machines, at least until developers at organisations like Intel and IBM started moving into multiple instruction, multiple data (MIMD) models.
Multicore architecture uses a single physical processor to incorporate the core logic of more than one processor, with the aim of creating systems that complete multiple tasks at the same time in the name of optimisation and better overall system performance.
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